The present invention generally relates to semiconductor devices and more particularly to a quantum semiconductor device formed on a generally tetrahedral etch pit that in turn is formed on a substrate having zinc blende structure such as InP or GaAs, as well as to the fabrication process thereof.
Electron devices used currently are mainly constructed upon a silicon substrate. A typical example is a DRAM (dynamic random access memory). In the field of DRAMs, intensive efforts are in progress for increasing the integration density. By now, an integration density of 256 Mbits is achieved, and it is expected that the integration density would reach 1 Gbits by the year 2000.
On the other hand, the prospect of the devices after the integration density of 1 Gbits reached is not clear yet. There is a concern that the operational principle of current MOSFETs may not be applicable in such extremely fine devices due to the wave nature of the carriers.
On the other hand, there are proposals for entirely new electron devices that operate based upon quantum effect. Such quantum semiconductor devices use quantum boxes (three-dimensionally confined quantum wells), quantum wires (two-dimensionally confined quantum wells) or one-dimensionally confined, ordinary quantum wells for the active part of the device. Particularly, the quantum devices are studied intensively in relation to the group III-V compound semiconductor devices.
Conventionally, however, such studies of quantum devices are mainly limited to conceptual studies directed to the feasibility of the device or theoretical aspects thereof, and the fabrication of actual quantum devices that include a uniform arrangement of quantum boxes has been neglected somewhat.
Currently, the only quantum device that can be fabricated with reliability is the one having a superlattice structure. In a superlattice structure, a number of thin layers each having a thickness of several tens of .ANG.ngstroms are stacked with each other to form one-dimensional quantum wells. Thus, there are proposals to fabricate quantum wires by forming two-dimensionally confined structures in such a superlattice structure by means of a photolithographic patterning process that uses an electron beam exposure process. Further, one may form quantum boxes by forming three-dimensionally confined structures in such a superlattice structure. See, for example, P. M. Petroff et al., Applied Physics Letters, vol.41, 1982, pp.635-638, or H. Temkin et al., Applied Physics Letters, vol.50, 1987, pp.413-415.
In such conventional processes for forming quantum wires or quantum boxes directly by applying photolithographic or electron lithographic processes, however, there occurs a problem of damage or contamination in the part where the desired quantum structure is to be formed. Thereby, the electronic or optical properties of the obtained device is inevitably deteriorated.
In order to eliminate the problem of damaging to the quantum structure at the time of fabrication, there is a proposal to form such quantum structures by depositing crystal layers. For example, it is proposed to form an insulation film of SiO.sub.2 or the like, on a single crystal semiconductor substrate, followed by a photolithographic patterning of the insulation film to form an insulation pattern. Thereby, the desired quantum wires or quantum boxes are formed by selectively growing semiconductor layers on such an insulation pattern by means of commonly used deposition process such as MOCVD process. See, for example, H. Asai, et al., Applied Physics Letters, vol.51, 1987, pp.1518-1520, or T. Fukui, et al., Applied Physics Letters, vol.58, 1991, pp.2018-2020.
Also, there are proposals to process a single crystal semiconductor substrate by means of a photolithographic process, followed by a deposition of semiconductor layers thereon by means of MBE (molecular beam epitaxy) or MOVPE (metal organic vapor phase epitaxy) process, to form the desired quantum wires or quantum boxes. In such an approach, a V-shaped groove is formed on a (100)-oriented surface of a III-V compound semiconductor substrate of GaAs or InP by using a SiO.sub.2 mask, followed by epitaxial deposition of semiconductor layers. See, for example, Kapon, E., et al., Applied Physics Letters, vol.50, 1987, pp.347-349.
However, these conventional proposals have not reached the point of reduction to practice with respect to how to form the quantum wires or quantum boxes.
In view of these situations, the inventor has previously proposed, in the Japanese Patent Application 6-92576, filed Apr. 28, 1994, a simple process for forming a quantum structure such as a quantum box on a substrate.
According to the proposal of the inventor, a mask of predetermined shape, which may have a circular opening, is provided on a {111}B-oriented surface of a substrate having zinc blende structure, such as GaAs or InP, followed by an anisotropic wet etching process to form an etch pit of an inverted tetrahedral shape. Further, a semiconductor layer of a widegap material acting as a barrier layer and a semiconductor layer of a small bandgap material acting as a quantum well layer, are deposited thereon alternately to form a quantum structure in the etch pit. In such a structure, it should be noted that a three-dimensionally confined quantum box is formed at the bottom apex of the etch pit. By using the foregoing process, formation of quantum structures suitable for an electron device, is substantially facilitated.
On the other hand, the foregoing process has a drawback in that one cannot obtain a groove suitable for a device when the process is applied to a semiconductor substrate having a {111}A-orientated surface. Further, the conventional process has a problem in that the process for forming the quantum well inevitably involves a step for exposing the etch pit thus formed to the air during the wet etching process. Thereby, contamination of the etch pit by the contaminants in the air is inevitable. Furthermore, such a wet etching process interrupts a series of continuous chain of processes conducted in a vapor phase deposition apparatus. Thereby, the throughput of fabrication is deteriorated also. It should be noted that a wet etching process is accompanied by a cleaning process and a drying process that has to be conducted outside the deposition apparatus.